Field of the Invention:
The present invention rleates to a gate array arrangement in complementary metal-oxide-semiconductor (CMOS) technology comprising basic circuits which are arranged on a chip at predetermined cell zones which consists of n-channel and p-channel transistors, where the transistors in the basic circuit are connected to one another in order to specify a fundamental function which is to be fulfilled and the fundamental circuits are connected to one another via wiring channels in order to fulfill functions.
Description of the Prior Art
Gate array arrangements are known, for example, from the Hitachi Review Vol. 33, No. 5, 1984, pp. 261-266. In such gate array arrangements, cell zones or cells are provided in a specific arrangement on a chip and basic circuits are constructed on the cell zones or cells. An example of a gate array arrangement of this type is disclosed in FIG. 1 in which the cell zones ZB are arranged in rows ZL in a core zone KB of a chip CH. Wiring channels VK are arranged between the rows ZL. Terminals TP and circuits of the type which cannot be constructed by way of the basic circuits can be provided on the exterior of the core zone chip.
The fundamental circuits consist of n-channel and p-channel transistors which are arranged in a specific manner in the cell zones ZB. By connecting the n-channel transistors and the p-channel transistors in each fundamental circuit, the fundamental circuit can be specified to fulfill a fundamental function and can be assigned, for example, a logic function or a storage function. It is set forth in the Hitachi Review, as referred to above, that a fundamental circuit can consist of, for example, ten transistors which are connected to one another in such a manner that a random access memory (RAM) storage cell having one input or two inputs is formed. By establishing other connections between the transistors in a fundamental circuit, it is possible to fulfill, for example, a logic function, for example NAND function.
It is necessary to connect the individual fundamental circuits in the gate array arrangement to one another in order to set up functions. This is carried out via wiring channels VK which extend between the rows ZL or which can also extend across the row ZL of the fundamental circuits.
Memories of differing capacity where previously constructed by a different method. For small capacity memory structures, bistable circuits were used. These consist of a plurality of gates and therefore require a relatively large number of fundamental circuits in a gate array to store one information unit. Large capacity memories were constructed by incorporating into the core zone of the chip a storage block of determinate capacity constructed as an overall cell. This meant that the capacity of a memory can be selected only within the stages of the storage capacity of the overall cell. Finally, the space requirement for such memories was relatively great since it was necessary to arrange wiring channels between the rows of cell zones.